A pipelined front-end, timing, and amplitude digitizing system

Abstract

A front-end digitizing system is needed for the straw tracking-detector of the MECO experiment. This detector has 24 000 channels of time and amplitude readout. The system operates in a high singles count-rate environment, and continuously digitizes the incoming pulses of every channel, using a latency buffer to temporarily hold this information. For each event, channel occupancy signals are sent to a local logic analyzer. Thus, the system can be self-triggered or triggered by a coincidence of the internally generated occupancy signal with an external gate. Upon presentation of a valid trigger, all data stored in the latency buffer are then read with zero-suppression to local RAM. The readout can provide sub-nanosecond timing and 6-9-bit amplitude resolution. This digitizer design will be implemented in an ASIC due to the large number of readout channels, the requirement that the data initially flow in parallel because of high single rates, and the large number of memory buffers. The digitizer is controlled by an FPGA, and the system clock can be varied between 15-60 MHz. This paper presents the conceptual design for the MECO readout system, but we anticipate that it can be used for many other applications requiring the acquisition of time and waveform signals in high counting rate environments.