A pipelined architecture for ray/bezier patch intersection computation

Abstract

An algorithm for computing ray/B ezier patch intersections is described from a hardware design perspective. This algorithm uses patch subdivision and other geometrical techniques to find a given maximum number of intersection points nearest to the ray origin. A pipeline-based hardware architecture is proposed, the number of pipeline stages required is verified by simulation, and the performance of a load-balanced implementation based on a state-of-the-art digital signal processor is estimated.