Abstract
A picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems is described. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5 K gate array LSI by developing fully digitally processes heat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, +or-3-ps linearity, zero-skew offset of +or-2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
