A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches

Abstract

Near-threshold voltage (NTV) digital VLSI circuits, though important, have their sequential elements vulnerable to soft errors. The critical charge for a single event upset for a D-latch depends on its fan-out load, supply voltage, and transistor level parameters. A SPICE simulation-based estimation of the critical charge is highly resource/time intensive. In this paper, we propose a physics-based semianalytical model to estimate the critical charge of a static D-latch as a function of its fan-out load, supply voltage, temperature, and transistor levels parameters. It can, therefore, be used while considering process voltage temperature (PVT) variations. The critical charge estimated by the model is in good agreement with SPECTER simulations with a maximum error of less than 3.4% employing STMicroelectronics 65-nm process design kit (PDK). We also validated the model at 32-nm technology node using technology computer-aided design (TCAD) mixed-mode simulations (a maximum error of less than 7.5% is observed). Using this model, we devise a methodology to estimate the critical charge using a few dc simulations and a single transient SPICE simulation for a given PDK. This is an end-to-end method to include an accurate estimation of the critical charge for latches in NTV standard cell library characterization.