Abstract
In the application of the Lambert W function, the surface potential for amorphous oxide semiconductor thin-film transistors (AOS TFTs) under the subthreshold region is approximated by an asymptotic equation only considering the tail states. While the surface potential under the above-threshold region is approximated by another asymptotic equation only considering the free carriers. The intersection point between these two asymptotic equations represents the transition from the weak accumulation to the strong accumulation. Therefore, the gate voltage corresponding to the intersection point is defined as threshold voltage of AOS TFTs. As a result, an analytical expression for the threshold voltage is derived from this novel definition. It is shown that the threshold voltage achieved by the proposed physics-based model is agreeable with that extracted by the conventional linear extrapolation method. Furthermore, we find that the free charge per unit area in the channel starts increasing sharply from the threshold voltage point, where the concentration of the free carriers is a little larger than that of the localized carriers. The proposed model for the threshold voltage of AOS TFTs is not only physically meaningful but also mathematically convenient, so it is expected to be useful for characterizing and modeling AOS TFTs.
Highlights
Amorphous oxide semiconductor thin-film transistors (AOS TFTs) such as zinc-oxide (ZnO) TFTs,[1] indium-gallium-zinc-oxide (IGZO) TFTs,[2] and indium-zinc-oxide (IZO) TFTs3 have emerged as one of the most promising candidates as switching/driving device in flat panel display (FPD) due to good uniformity, high mobility, transparency, flexibility and good process compatibility with hydrogenated amorphous silicon TFTs (a-Si: H TFTs)
For the conventional a-Si: H TFTs, even though a large bias is applied to the gate, the Fermi level is still pinned near the envelope of tail states due to huge density of states (DOS) existing in conduction band tail
This paper proposes a physics-based model of threshold voltage for AOS TFTs
Summary
Amorphous oxide semiconductor thin-film transistors (AOS TFTs) such as zinc-oxide (ZnO) TFTs,[1] indium-gallium-zinc-oxide (IGZO) TFTs,[2] and indium-zinc-oxide (IZO) TFTs3 have emerged as one of the most promising candidates as switching/driving device in flat panel display (FPD) due to good uniformity, high mobility, transparency, flexibility and good process compatibility with hydrogenated amorphous silicon TFTs (a-Si: H TFTs). The threshold voltage of a-Si: H TFTs is generally defined as the gate bias where the Fermi level moves into the conduction band tail.[4,5,6] With regard to AOS TFTs, their subgap DOS is 2-3 orders of magnitude smaller than that of a-Si: H TFTs in conduction band tail.[7] The Fermi level in the channel of AOS TFTs may be pulled up to the bottom of conduction band (EC) at a large gate bias, where free charges are dominated over localized charges.[8] the definition of Vth for AOS TFTs will be quite different from that for a-Si: H TFTs. Various methods have been proposed to extract threshold voltage from transfer characteristics for AOS TFTs. Thereinto, the extrapolation method is the most commonly used, in which Vth is extracted as the gate voltage axis intercept of the linear extrapolation in the linear region.[9] In Ref. 10, Vth is extracted by the constant-current method, which defines Vth as the gate bias at a certain drain current. The calculated value of Vth is confirmed to be consistent with that extracted from experimental data
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