Abstract
SummaryA phase detector (PD) is a key element in the structure of phase‐locked loops (PLLs) and, in particular, of PLL‐based clock and data recovery circuits (CDRs). Thanks to their good properties in terms of robustness and ease of design, bang‐bang PDs (BBPDs) are the most common choice for the implementation of a PD in such systems. The operation of BBPDs is typically modelled only in terms of the phase difference between their inputs; however, this approach is not sufficient to describe their dynamic behaviour completely. To address this issue, this paper introduces a more comprehensive model of the operation of BBPDs that takes into account phase as well as frequency differences between their inputs, leading to a two‐dimensional description of the output of BBPDs. Numerical simulations of the operation of a CDR have been realised to evaluate the validity of the model. Copyright © 2013 John Wiley & Sons, Ltd.
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