A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop

Abstract

A phase-interpolator-based fractional counter (PIFC) is proposed to reduce power consumption by replacing TDC in a ring-oscillator-based digital fractional-N phase-locked loop. A predicted-phase-interpolation method is used to calculate the integer and fractional parts of the frequency-division-ratio and to find two interpolation clocks; the prediction method gives a significant power reduction in the proposed PIFC by enabling the use of low-frequency clocks for phase interpolation. The proposed PLL chip in a 65-nm CMOS occupies 0.173 mm2 and consumes 15.5 mW at 6 GHz and 1.2 V; the PIFC consumes less than 20% of the TDC power. The integrated rms jitter is 1.75 ps and a FoM value of −223.2 dB is achieved.