A Performance model for accelerating scientific applications on reconfigurable computers

Abstract

With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applications, such as those in scientific computing. There has been a resulting development of reconfigurable computers--computers which have both general purpose processors and reconfigurable hardware, as well as memory and high-performance interconnection networks. Oftentimes, reconfigurable hardware can provide fantastic speed-ups for kernels in a scientific application but when the kernels are integrated back into the complete application, the overall speed-up is not very impressive. To address this problem, we have developed a simple performance model for reconfigurable computers to facilitate the accurate evaluation of whether or not the speed-up that will be achieved by implementing an application on a reconfigurable computer justifies the implementation effort and cost. The proposed performance model captures the main features of reconfigurable computers: one or more general purpose processors; reconfigurable hardware for acceleration; memory, spread over multiple banks, that is local to the reconfigurable hardware; and limited bandwidth between the general purpose processors and the reconfigurable hardware. It also captures issues of concern for using the reconfigurable hardware, such as the relationship between off-chip memory and the amount of parallelism in a design. We have used the model to predict the performance of an implementation of a molecular dynamics simulation on an SRC 6e MAPstation. The error between the predicted performance and the actual performance is only 3.5%.