A performance analysis of dispatch rules for semiconductor assembly & test operations

Abstract

The purpose of this paper is to statistically compare six dispatch rules for semiconductor assembly & test operations with respect to two hierarchical objectives: minimise the weighted sum of key device (chip) shortages and maximise the weighted throughput of lots processed. Three factors affecting system performances are studied: the different rules, whether the machines are set up at time zero, and whether the maximum number of changeovers is restricted over the planning horizon. System performance is determined with both a discrete event AutoSched AP simulation model and a greedy randomised adaptive search procedure (GRASP) for 30 real and randomly generated data sets. A full factorial design with common random numbers was conducted to concurrently investigate the interaction among the three factors. The statistical analysis showed that the two rules designed to process as many hot lots (i.e., key device lots) as possible performed the best in minimising the weighted shortage. We also found that initial setups and limiting the number of setups over a 2- to 3-day planning horizon can significantly weaken the rules’ performance but in some cases the interaction of these factors mitigated their negative impacts. Due to the general nature of the models, the results should be applicable to most reentrant flow shops. The GRASP is now being used by the sponsoring company and the most promising dispatch rules are being studied in an experimental environment.