Abstract
The architecture of the data acquisition system foreseen for the LHCb upgrade, to be installed by 2018, is devised to readout events trigger-less, synchronously with the LHC bunch crossing rate at 40 MHz. Within this approach the readout boards act as a bridge between the front-end electronics and the High Level Trigger (HLT) computing farm. The baseline design for the LHCb readout is an ATCA board requiring dedicated crates. A local area standard network protocol is implemented in the on-board FPGAs to read out the data. The alternative solution proposed here consists in building the readout boards as PCIe peripherals of the event-builder servers. The main architectural advantage is that protocol and link-technology of the event-builder can be left open until very late, to profit from the most cost-effective industry technology available at the time of the LHC LS2.
Highlights
The LHCb experiment is designed to perform high-precision measurements of CP violation and search for New Physics by exploiting the decays of the beauty and charm hadrons copiously produced at the LHC
The readout solution based on PCI Express (PCIe)-3, currently under study as an alternative solution to the ATCA-based readout, consists of developing the LHCb readout boards as PCIe generation 3 (PCIe-3) standard boards, named PCIe40, which act as add-on cards in the motherboards of the High Level Trigger (HLT) eventbuilder servers
The PCIe hard IP blocks available in the FPGAs are generally very efficient: one 8-lane block uses less than 1% of the resources
Summary
The LHCb experiment is designed to perform high-precision measurements of CP violation and search for New Physics by exploiting the decays of the beauty and charm hadrons copiously produced at the LHC. LHCb is expected to take in excess of 8 fb−1 by 2018 by recording data at a constant luminosity of 4. × 1032 cm−2s−1 (twice the design luminosity and more than a factor four the average number of interactions per crossing at μ = 1.5). The amount of beauty and charm quarks generated by LHC will double, while the pileup of the events will reduce by a factor two. The limited detector data available to the HLT trigger would limit the physics yield for hadronic decays even at higher trigger rates. In order to remove these design limitations we plan to upgrade the spectrometer by 2018. The strategy for the upgrade consists of in removing the first-level hardware trigger
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