Abstract
This paper presents a power-efficient RF differential receiver front-end supporting transmitted-reference (TR) communication in a 90 nm CMOS technology. Particularly, it addresses the issues of designing the frontend amplifier with low-noise and passive matching circuits on a silicon process and integrating a low-power delay unit in the front-end with wideband characteristics. The proposed architecture includes a differential high simulated gain (11 dB) amplifier which is centered at 21.6 GHz (in the K-Band) with a 6.2 GHz bandwidth (18.1~24.3 GHz). The input and output reflection parameters have centered values around -26 and -18 dB, respectively. With noise matching, the amplifier achieves 2.6~2.9 dB bandwidth noise-figure and 2 dBm input power limit for linear coverage. To interface the amplifier with a following RF mixer, a submicron delay-block (DB) is proposed with provision of adjusting number of stages in the delay chain. The branched DB architecture achieves monotonic delays covering a range of 70-800 ps (including group-dispersion). Tweaking of delay is possible through four design parameters and the set-up is analyzed by extending the number of cascaded stages up to eight. Driven from a 1.2 V supply, the amplifier and the DB consume 13.9 and 8.52- 10.61 mW power, respectively, and realize the circuits for the TR front-end. When compared with simulated results of reported CMOS receivers, the proposed design delivers higher performance in terms of a microwave figure-of-merit.
Highlights
In recent literature, on-chip wireless interconnects have been reported as alternatives to traditional metallic inter-chip communication which becomes possible due to scaling down of CMOS integrated circuits [1], [2], [3]
A UWB receiver front-end with an integrated antenna can facilitate this process by moving the transmission system to a wireless domain [5]
Wideband Differential Front-end As the first section of the proposed TR-receiver front-end, the design parameters of the differential wideband low noise amplifier are analyzed with the CMOS process
Summary
On-chip wireless interconnects have been reported as alternatives to traditional metallic inter-chip communication which becomes possible due to scaling down of CMOS integrated circuits [1], [2], [3] In this regard, ultra-wideband (UWB) transmission has been cited as a standard which could facilitate chip-scale wireless communication for short-distance low-power applications [4]. The wideband nature of a UWB receiver can offer additional benefits like provision to include multiple access capability and greater resistance against interference and multipath fading [6], [7], [8] To avail these opportunities, the Federal Communications Commission has decided to allow UWB transceivers to operate in frequency ranges shared by other networks as low power density of UWB does not create interference in overlapping bands [9].
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