A Parameterizable NoC Router for FPGAs

Abstract

The Network-on-Chip (NoC) approach fordesigning (System-on-Chip) SoCs is currently used forovercoming the scalability and efficiency problems of traditional on-chipinterconnection schemes, such as shared buses and point-to-point links. NoCdesign draws on concepts from computer networks to interconnect IntellectualProperty (IP) cores in a structured and scalable way, promoting design re-use.This paper presents the design and evaluation of a parameterizable NoC routerfor FPGAs. The importance of low area overhead for NoC components is pivotal inFPGAs, which have limited logic and routing resources. We obtain a low arearouter design by applying optimizations in switching fabric and dual purposebuffer/connection signals. We utilize a store and forward flow control withinput and output buffering. We proffer a component library to increase re-useand allow tailoring of parameters for application specific NoCs of varioussizes. The proposed router supports the mesh architecture which is well knownfor its scalability and simple XY routing algorithm. We presentIP-core-to-router mapping strategies for multi-local port routers that enableample opportunity to optimize the NoC for application specific data traffic. Aset of experiments were conducted to explore the design space of the proposedNoC router using different values of key router parameters: channel width (flitsize), arbitration scheme and IP-core-to-router mapping strategy. Area andlatency results from the experiments are presented and analyzed. These resultswill be useful to designers who want to implement NoC on FPGAs.