A Parallel Topology Based Power-Stage PMSM Emulator With Accurate Ripple Current Reproduced

Abstract

As a power hardware-in-the-loop (PHIL) technology, the power-stage motor emulator (ME) can be employed for the port characteristics emulation of motors. Meanwhile, the ripple current reproduction is one of the key technologies for achieving the high precision emulation of the port characteristics. Commonly, the high requirement for the hardware topology and the modulation strategy with rapid response and low harmonics are the main challenges. Aiming to obtain the precision ripple current, a ME scheme with dual-branch parallel topology is proposed in this paper, of which the equivalent switching frequency can be increased greatly by mean of interleaving switch. Furthermore, a new three-level space vector modulation strategy based on the idea of virtual transformation is presented. With the proposed strategy, the dual-branch parallel topology can be equivalently transformed into a specific three-phase three-level back-to-back topology. Finally, simulation and bench experiments have been conducted to validate the effectiveness of the proposed scheme. The results indicate that the proposed topology combined with the modulation strategy has a superior performance in improving the ripple current tracking accuracy of ME. Moreover, the proposed method can provide an excellent insight into improving the emulation accuracy of motor characteristics in practical applications.