A parallel series approximation scheme for a fast floating point divider

Abstract

This paper introduces a high-speed hybrid floating-point division method which uses an accurate piecewise linear approximation and parallel power-series iteration. The division process starts by getting an initial reciprocal approximation of the divisor from a reciprocal unit and calculating the quotient by successive iterations. To speed up the division process, the dividend is partitioned into two groups of bits and the quotient for each group is formed in parallel. By using 14 bits to the right of the binary point of the divisor to address the look-up table, the error of the initial approximation is less than 2/sup -28/. Therefore, for 64-bit (53-bit fraction) floating point operation only one more iteration is required. The final quotient, which is obtained by adding the two quotients in each group, is 55-bit precision before rounding. The error, which is involved in the first quotient calculation, is effectively cancelled by adding a correction term into the second dividend before the second quotient is calculated. No special rounding is required to support four rounding modes in the IEEE-754 standard since the exact quotient is obtained with no errors and the exact remainder can be produced. Therefore, the rounding is straightforward. The latency of this division operation is 5 cycles when using a single cycle add-multiply unit. This algorithm finds application in fast and accurate floating-point division.