A parallel processing architecture for two dimensional discrete wavelet transform without using multipliers

Abstract

The Discrete Wavelet Transform is well known for its applications in image and video compression. Due to its remarkable advantage over the discrete cosine transform (DCT) in image compression, 2-D DWT has been accepted for the JPEG-2000 compression standard. The implementation of 2-D DWT, however, is highly computation-intensive and many of its applications demand real-time processing. The Lifting Scheme is an efficient implementation of Wavelet Transform. Using the Lifting Scheme, it is easy to use integer arithmetic without encountering problems due to finite precision or rounding. Design of multipliers is a complex task and will consume lot of hardware space. So here we have used an arithmetic shift and add approach to simplify the process and thereby save the hardware space utilized. Nowadays, most of the applications require real-time DWT engines with large computing potentiality for which a fast and dedicated very-large-scale integration (VLSI) architecture appears to be the best possible solution. While it ensures high resource utilization, that too in cost effective platforms like field programmable gate array (FPGA), designing such architecture does offer some flexibilities like speeding up the computation by adopting more pipelined structures and parallel processing, possibilities of reduced memory consumptions through better task scheduling or low-power and portability features.