A parallel packet switch with multiplexors containing virtual input queues

Abstract

A packet switch with parallel switching planes is a parallel packet switch (PPS). A PPS can scale-up to faster line speeds than can a single-plane switch. It is an open problem to design a PPS that is feasible to implement using existing low-cost hardware components where no component runs faster than line speed. A PPS must be able to internally load balance traffic, have packet delays comparable to a reference single-plane switch, and provide QoS (bandwidth, delay, and loss guarantees) to flows. We investigate a new architecture for a PPS that uses virtual input queues (VIQ) in the output multiplexors to achieve packet-level load balancing. A VIQ at an output multiplexor consists of one FIFO queue for each input. For K planes and N ports, our VIQ PPS requires KN cells of buffering in the input demultiplexors and 2 NK+2 K cells of buffering in the output multiplexors to achieve guaranteed loss-free operation and in-order cell delivery. Using simulation models, the new VIQ PPS is shown to offer improved delay performance compared to existing PPS designs. For balanced and unbalanced loads the VIQ PPS is stable where a reference iSLIP single-plane switch is unstable.