A parallel multiple hashing architecture for IP address lookup

Abstract

Address lookup is one of the main functions of the Internet routers and a very important feature in evaluating router performance. As the Internet traffic keeps growing and the number of routing table entries is continuously growing, efficient address-lookup mechanism is essential. In recent years, various fast address-lookup schemes have been proposed, but most of those schemes are not practical in terms of the memory size required for routing table and the complexity required in table update. In this paper, we have proposed a parallel IP address lookup architecture based on multiple hashing. The proposed scheme has advantages in required memory size, the number of memory accesses, and table update. We have evaluated the performance of the proposed scheme through simulation using data from MAE-WEST router. The simulation result shows that the proposed scheme requires a single memory access for the address lookup of each route when 203 kbytes of memory and a few-hundred-entry TCAM are used.