Abstract
Cycle-based simulation at register-transfer- and gate level realized by a Levelized Compiled Code (LCC) technique represents a well established method for functional verification in processor design. Due to rapidly increasing design sizes, simulation acceleration is an important issue. We present a parallel LCC simulation system that has been developed to run on loosely-coupled systems. It comprises three parallel simulators and a complex model partitioning environment. An essential idea of our parallelization approach is to valuate circuit model partitions with respect to the expected parallel simulation run-time and to integrate corresponding cost functions into partitioning algorithms. This is done on the basis of a formal model of parallel LCC simulation. In this paper, we focus on the strong relation between model partitioning and the parallel simulation technique chosen. The components of the simulation system are outlined and experimental results with respect to simulation acceleration are given for IBM processor models of different size.
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