A parallel hierarchical algorithm for module placement based on sparse linear equations [VLSI layout

Abstract

We present a fast and effective module placement algorithm which is based on the PROUD algorithm. The PROUD algorithm uses a hierarchical decomposition technique and the solution of sparse linear systems of equations based on a resistive network analogy. It has been shown that the PROUD algorithm is suitable for solving the placement problem for very large circuits, and obtains placement qualities that are comparable to the best placement algorithms based on simulated annealing, but is several orders of magnitude faster. In this paper, we first report on an improved hierarchical placement algorithm which is based on perturbing the matrices in the matrix equation solution stage of the PROUD algorithm. The new modified PROUD algorithm performs much faster that the original PROUD algorithm. We subsequently propose parallel versions of the original and modified algorithms that combine both fine grain and coarse grain parallelism to obtain another order of magnitude improvement in the runtime without loss of the quality of the layout. Results are reported using MPI on various multiprocessor systems for a variety of large layout benchmark circuits.