Abstract
This paper presents a novel approach to solve the VLSI channel and switchbox routing problems. The approach is based on a parallel genetic algorithm, GAP, which runs on a distributed network of workstations. Our algorithm optimises both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled capacitance). We show that our parallel approach outperforms traditional sequential genetic algorithms when applied to these routing problems. An extensive investigation of the parameters of our algorithm yields routing results that are qualitatively better or as good as the best published results.
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