A Packet Classifier Using Parallel EVMDD (k) Machine

Abstract

A decision diagram machine (DDM) is a special-purpose processor that uses special instructions to evaluate a decision diagram. This paper presents a packet classifier using a parallel edge-valued multi-valued decision diagram (EVMDD (k)) machine. To reduce computation time and code size, first, a rule set for the packet classifier is partitioned into groups. Then, the parallel EVMDD (k) machine evaluates them. We implemented the parallel EVMDD (k) machine consisting of 32 EVMDD (4) machines on an FPGA, and compared it with the Intel's Core~i5 microprocessor running at 1.7GHz. Our machine is 7.8-40.1 times faster than the Core~i5, and it requires only 12.0-52.6 percents of the memory for the Core~i5.