Abstract

A novel Via-Hole plated heat sink (PHS) structure with an improved gate-packing density is developed for K-band GaAs power FET's. The gate-packing density in this structure is increased to four times greater than that in the conventional direct via-hole structure, by making via-holes under the source-grounding pads fabricated outside the FET active area. The increase in the gate-packing density allows the design of a high-power, high-frequency FET with a larger gate periphery. The resultant 2.4-mm gate periphery device with 0.7µm gate length delivered 1.1 W (30.4 dBm) of output power with 5.0-dB gain and 19.2-percent power added efficiency at 20 GHz, and exhibited 0.74 W (28.7 dBm) at 30 GHz. The same type of device assembled in the hermetically sealed package delivered 1.0 W (30 dBm) of output power with 4.8-dB gain and 13-percent power added efficiency at 20 GHz. Thermal and mechanical-environmental tests were made to assess the reliability of the novel Via-Hole PHS FET. Results showed no failure nor significant change in device parameters throughout the tests.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call