Abstract
A spur-reduction technique is presented to achieve low fractional spurs for a 5–10 GHz frequency synthesizer. A wideband fractional-N frequency synthesizer is designed with digital multi-stage noise shaping (MASH) Delta-Sigma Modulator (DSM). The third-order MASH Structure (MASH 1-1-1) is optimized using FPGA for spur-reduction. It exhibits in-band fractional spur of −66.85dBc/Hz at 50 kHz offset and improved about 18dBc/Hz at 9 GHz. The theory of Fractional-N frequency synthesizers is also presented.
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