Abstract
Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.
Highlights
To develop reliable circuits, a traditional synchronous circuit must have a large timing margin to ensure the correct operation under worst-case timing conditions
To minimize the timing margins, many techniques have been proposed for tolerating a timing error that happens in the circuit with the minimal margin
In the waveform viewer are the data values which are captured by error detection and correction flip-flop (EDACFF) and traditional FF at the first, the second, the third, and the four stages of the pipeline, respectively
Summary
A traditional synchronous circuit must have a large timing margin to ensure the correct operation under worst-case timing conditions. It means that an appropriate timing margin is added to a clock period to cover the worst-case circuit propagation delays. Among most of the circuit operation time, the worst-case timing margin is not fully used since the worst-case rarely happens in practice. The worst-case timing margin causes higher throughput loss and lower energy efficiency of a design in typical- or best-case conditions. To minimize the timing margins, many techniques have been proposed for tolerating a timing error that happens in the circuit with the minimal margin. The techniques can be categorized into two groups: timing error prediction (TEP), and error detection and correction (EDAC)
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