A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter

Jin-Wook Kang,Hoon Lee,Seung-Wook Hyun,Jung-Hyo Lee,Yong Kan

doi:10.3390/electronics9122195

Abstract

This paper proposes a novel pulse width modulation (PWM) for a three-level neutral point clamped (NPC) voltage source inverter (VSI). When the conventional PWM method is used in three-level NPC VSI, dead time is required to prevent a short circuit caused by the operation of complementary devices on the upper and lower arms. However, current distortion is increased because of the dead time and it can also cause a voltage unbalance in the dc-link. To solve this problem, we propose a zero dead-time width modulation (ZDPWM) which does not require dead time used in complementary operation. The proposed technique applies the offset voltage to the space vector pulse width modulation (SVPWM) reference voltage for the same modulation index (MI) as the conventional SVPWM, but any complementary switching operation needs dead time. In addition, the proposed method is divided into four operation sections using the reference voltage and phase current to operate switching devices which flow the current depending on the section. This ZDPWM method is simply implemented by carrier and reference voltage that reduce the current distortion, because complementary operation that needs dead time is not implemented. However, the operation section is delayed due to the sampling delay that occurs during the experiment. Therefore, in this paper, we conduct a modeling of sampling delay to improve the delay of operation section. To verify the principle and feasibility of the proposed ZDPWM method, a simulation and experiment are implemented.

Highlights

In high power applications such as medium voltage motor drives, solar cells, vehicles, and most recently, wind generation system, etc., multilevel topologies introduced in [1] have been widely applied to reduce harmonic in the grid current, to downsize the physical filter size, and to mitigate the switching losses of the used devices as compared with the conventional two-level pulse width modulation (PWM)inverter
We suggest an improved method that can solve the sampling delay of a microcontroller unit (MCU) that is seen in the experiment
In order to figure out the dead-time effect, grid side current, LCL filter current, and motor current are shown on Figure 16

Summary

Introduction

In high power applications such as medium voltage motor drives, solar cells, vehicles, and most recently, wind generation system, etc., multilevel topologies introduced in [1] have been widely applied to reduce harmonic in the grid current, to downsize the physical filter size, and to mitigate the switching losses of the used devices as compared with the conventional two-level pulse width modulation (PWM)inverter. In high power applications such as medium voltage motor drives, solar cells, vehicles, and most recently, wind generation system, etc., multilevel topologies introduced in [1] have been widely applied to reduce harmonic in the grid current, to downsize the physical filter size, and to mitigate the switching losses of the used devices as compared with the conventional two-level pulse width modulation (PWM). The capacitor used in FC requires precharging, and the high number of flying capacitors required with increasing output levels reduces system reliability. The disadvantages of CMLI are the complexity of synchronization and the unbalanced power losses between power modules. Among these topologies, the three-level neutral point clamped (NPC) voltage source inverter

Methods

Results

Conclusion