A Novel Virtual Channel Implementation Technique for Multi-core On-chip Communication

Abstract

In this paper, a new approach for implementing virtual channels (VC) for multi-core interconnection networks is presented. In this approach, the flits of different packets interleave in a channel with a single buffer of nominal depth by using a rotating flit-by-flit arbitration. The routing path of each flit is guaranteed because the flits belonging to the same packet are attached with an ID tag at each router so that they are differentiable at downstream routers. We present this on-chip communication of packets through sharing of channel and buffer, which is a novel method of virtual channel implementation. Furthermore, we demonstrate it by adding arbitrary virtual channels depending on the number of packet requests for a physical channel. In this way, NoC (Network-on-Chip) contention can be removed cheaply. Moreover, we discuss contention free communication where the depth of shared buffer does not affect the performance. A contention-free communication with small (one) buffer depth can create an efficient on-chip communication with high performance, small chip area and low power consumption.