Abstract
In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on both Xilinx Spartan-6 and Artix-7 devices and the resulting design flows which allow to accurately balance the nominal delay of the different signal paths is outlined. The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation are able to fit in just 32 Configurable Logic Blocks (CLBs) without sacrificing steadiness, uniqueness and uniformity, thus outperforming most of the previously published FPGA-compatible PUFs.
Highlights
The usage of dependable devices such as smartphones, PCs, tablets, smart-cards and digital tokens is nowadays omniscient
The inter-class Hamming Distance (HD) of the Xilinx Spartan-6 pool is shown in Figure 10a, with values on the x-axis reported as percentage among 128-bit responses
We presented a novel ultra-compact Physical Unclonable Function (PUF), the Delay Difference PUF (DDPUF)
Summary
The usage of dependable devices such as smartphones, PCs, tablets, smart-cards and digital tokens is nowadays omniscient. Physical Unclonable Functions (PUFs) have played an important role as hardware’s protection mechanism for generation of identification strings and cryptographic keys [1]. By exploiting process variations and mismatch, PUFs can generate a “fingerprint” that can be used as cryptographic key or unique identifier for (physical instance of) a device [3]. Reverse-engineering of PUF-based devices can be not trivial due to unpredictability of manufacturing process variations This particular feature has given birth to new PUF-related security applications, such as intellectual property protection, cloning/counterfeiting prevention and complex security-on-chip design [4,5,6,7,8]. This phenomenon can arise in Arbiter PUFs as reported by [20], and an extra effort has to be spent to mask the bit-cells that present unwanted features
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