Abstract
The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard “gate-driven” (GD) control of MOS transistors and is designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional “bulk-driven” (BD) control of active devices in the circuit. Each presented circuit topology has its own pros and cons. However, both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, wide temperature range (from −20 °C to 85 °C) and for random process variations as well. Both presented comparator designs can reliably operate with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on chip prototypes.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: AEU - International Journal of Electronics and Communications
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.