A novel Time-to-Digital Converter for All Digital Phase-Locked Loop

Abstract

This paper presents a new design of a two-step Time-to-Digital Converter (TDC), which reduces the complexity of the circuits, and the power consumption and area of the circuit. The on-line self-calibration method for the time amplifier (TA) without any other calibration circuits is proposed to solve the nonlinearity of the TA. For PVT variation, the delay cells of the first stage and second stage is calibrated according to the output bits and the gain of TA. The TDC in this paper consumes 0.17mW with 1ps resolution using the 16nm PTM model, and the DNL and INL are less than 1LSB.