A Novel Technique to Produce Logic ‘1’ in Multi-threshold Ternary Circuits Design

Abstract

Nowadays, due to the high capabilities of nanotechnology in designing multi-valued logic (MVL) circuits, much research has been done to design MVL circuits in nanotechnology. The use of MVL circuits reduces chip interconnections, thereby decreasing the chip area and power consumption. Various methods have been proposed to produce logic ‘1’ in the ternary logic circuits; these include the use of voltage division on VDD and application of two supply voltages. The use of two supply voltages increases the interconnections, which is against one of the multi-valued logic aims, and using voltage division on VDD can cause considerable static power dissipation. In this paper, based on the multi-threshold voltage of CNFET, the circuits are designed to charge a load capacitor to VDD/2 or discharge to VDD/2 in order to produce logic ‘1’ by a novel structure of diode-connected transistors. Thus, with the use of the single-supply voltage, the direct current is eliminated and the static power consumption is dropped sharply. As expected, the simulation results show that the proposed designs have considerably low power consumption with the same delay; thus, they offer a considerably lower PDP in comparison with other single-supply designs with the same noise margin.