A Novel Technique for Input Vector Compression in System-on-Chip Testing

Abstract

A software based hybrid test vector compression technique for testing system-on-chip integrated circuits using an embedded processor core was previously discussed by the authors. In this approach, a software program is loaded into the on-chip processor memory along with the compressed test data sets. To minimize on-chip storage besides testing time, the test data volume is first reduced by compaction in a hybrid manner before downloading into the processor. The proposed method utilizes a set of adaptive coding techniques for realizing lossless compression. The compaction program need not be loaded into the embedded processor, as only the decompression of test data is required for the automatic test equipment. The developed scheme necessitates minimal hardware overhead, while the on-chip embedded processor can be reused for normal operation on completion of testing. As an extension of this prior work, this paper reports further results on studies of the problem based on the use of Limpel-Ziv-Walsh coding besides Burrows-Wheeler transformation and demonstrates the feasibility of the suggested methodology with simulation results on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits.