Abstract

Common-mode current is one of the major challenges in transformerless grid-connected photovoltaic (PV) inverters. This current is affected when the PV arrays are exposed to different environmental conditions and its value increases. This paper attempts to investigate the effect of mismatched condition on voltage balance of PV arrays, which leads to the increment of common-mode current. A new circuit structure is presented for compensating for voltage drop caused by partial shading and ambient temperature and removing the effect on the common-mode current. To validate the proposed structure, a laboratory prototype of this circuit is implemented.

Highlights

  • In recent years, grid-connected photovoltaic (PV) systems have become increasingly significant due to rising prices of fossil fuel, sustainability of solar energy, and its reliability

  • The PV arrays are divided into two equal parts and their midpoint is connected to the middle of the separate DC link capacitors

  • A DC/DC converter might be located between the arrays and inverter. e benefit of the second method over the first one is its separate and accurate control of each of the array sections, which causes the improvement of the maximum power point tracking (MPPT) [6, 7]

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Summary

Introduction

Grid-connected photovoltaic (PV) systems have become increasingly significant due to rising prices of fossil fuel, sustainability of solar energy, and its reliability. A major challenge in connecting PV arrays to the power grid through transformerless inverters is the common-mode current. It flows through parasitic capacitors and is located between photovoltaic arrays and ground, which leads to some major issues [19, 20]. It causes loss increase, quality reduction of the injected current to the grid, electromagnetic interference, inaccurate performance of the protective relays, and especially some issues related to the personal safety [21, 22]. A common-mode reduction method is to connect grid negative terminal to the midpoint of DC link capacitors, which causes a constant common-mode voltage equal to half of input value [27]. VDM causes generation of additional common-mode voltage (VCM_DM) and influences on common-mode current which is obtained as [30]

A L1 Inverter
Circuit Performance in Normal Condition
L1 A B Grid
Circuit Performance under Mismatch Condition
D S1 S2 L3
Switching Method
Stability
L2 c 3 C2
Reliability
Simulation and Experimental Results
Conclusion
Full Text
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