A Novel Stateful Logic Device and Circuit for In‐Memory Parity Programming in Crossbar Memory

Abstract

AbstractAs one application of stateful logic computation in crossbar array, a in‐array parity programming method is proposed. A single programming step within the array can simultaneously program and store a parity bit right adjacent to the data bits, minimizing the overhead from a complex parity calculation and transfer process from outside of the array. Sensing on the basis of a gray code for a multi‐bit memristor is the key enabler for generating an even or odd parity. A memristor device that features an altering resistance switching behavior according to monotonous change in electrical bias size, complementary resistive switching (CRS), is deployed to improve data per parity ratio. A step‐by‐step derivation of the array scheme optimal for this purpose is shown through margin analysis. A simulation based on the experimental parameters of a 2‐bit per CRS parity cell proves that the proposed current driven scheme enables an output voltage linearization on the parity cell node with varying resistance states of 6‐bit data cells while meeting the voltage requirements of both the parity and data cells. Such in‐memory parity programming is thought to improve the robustness of current crossbar memory technology with the miniscule overhead, further extending the versatility of the in‐memory logic applications.