A novel SOI LDMOS with a Trench Gate and Field Plate and Trench Drain for RF applications

Abstract

In this paper a novel structural silicon on insulator (SOI) LDMOS with trench gate and field plate and trench drain (TGFPTD) is firstly proposed. The proposed TGFPTD SOI LDMOS is mainly characterized of a vertical channel and channel current spreading area, a lateral drift region, a field-stopping doped area, a trench drain as well as nearly the most homogenous current flowing through the drift region. Therefore it is convinced that the proposed TGFPTD SOI LDMOS cell is featured of much lower on-resistance, lower on-state voltage drop and power dissipation, higher breakdown voltage and higher switching speed than those of conventional SOI LDMOS. Simulated results obtained with TCAD tools indicate that the proposed TGFPTD SOI LDMOS cell could be realized to some extent in advanced CMOS technologies and is characterized of low on-state voltage drop, low on-state static resistor and high off-state breakdown voltage.