Abstract
A novel Sobel edge detection accelerator based on reconfigurable architecture is proposed to solve the problem of low power-to-performance ratio of traditional Sobel edge detection algorithm in CPU processing. The accelerator adopts pixel level fine grain image data parallel processing and row buffer storage architecture to improve the processing efficiency of edge detection. At the same time, a reconfigurable architecture based on FPGA is built. Through experiments, it can be found that the acceleration effect of the edge detection accelerator on video data is superior to that of the CPU software. Compared with similar accelerators, the acceleration performance of the novel accelerators improves by 10%. The results show that the proposed edge detection accelerator can be used in embedded systems to provide edge detection processing capability with high performance power consumption ratio.
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