A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator

Chi Xu,Yu Jin,Duli Yu

doi:10.1155/2017/9861383

Abstract

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

Highlights

A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop IntegratorThis paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field
This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, extending the integer-order Sigma-Delta modulator to a non-integer-order one in the Sigma-Delta ADC design field
Sigma-Delta modulator technology has been commonly used in various fields including inertial sensors, such as the MEMS accelerometer and gyroscope [1,2,3]

Summary

A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; the signal-to-noise ratio (SNR) is improved remarkably. A 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator

Introduction

Mathematical Model of the Sigma-Delta Modulator System

Fractional-Order Sigma-Delta Modulator System

PSO Algorithm for Fractional-Order Sigma-Delta Modulator

Simulation

Conclusions