A Novel Semi-MASH Sub-stage for High-order Cascade Sigma-Delta Modulators

Abstract

This paper presents a novel architecture for a high-order cascade oversampling modulator: semi-MASH based on the application of stage feedback within each stage and using appropriate error cancellation logic to spread the noise transfer function (NTF) zero to extend the signal-to-quantization noise ratio (SNQR). Moreover, minimum-noise-shaping-per-stage keeps 0dB overload region regardless of the stage number. An 8/spl times/OSR 5th order 1.5-bit semi-MASH design (1+1-1+1-1mb) is presented as an example achieving 81 dB peak SNQR and 88 dB SFDR. More than 14 dB SNQR and 12 dB SFDR are gained by spreading the NTF zero. Behavioral simulations with MATLAB and SIMULINK demonstrate the good performance of the proposed architecture.