A novel scheduling algorithm for phase change memory based main memory system with multiple ranks

Abstract

Conventional main memory systems made of DRAM are hitting power, cost and scalability limits. Many non volatile memory technologies like phase change memory are now strong competitors for DRAM due to their higher density but are inferior in terms of latency. Non uniform latencies of memory devices affect the overall memory access latency. Reordering mechanisms are hence used to change the memory access patterns in order to reduce the overall memory access latency. To reduce access latency we propose a new scheduling policy to introduce reordering among memory requests so that the higher latencies of non volatile memories are hidden. Latency comparisons to existing DRAM main memory and a similar phase change memory are made. The proposed scheme uses a memory that is designed to be distributed into many ranks but the product of banks and ranks remains same across all three memory systems used in the comparison. Reads have higher priorities than writes and reads targeted to the same location in memory as an earlier write are serviced immediately. The proposed scheme is very close to DRAM main memory with a latency of 1.37× (on average), and faster than existing PCM main memory with a latency of 0.744× (on average).