A novel scheduler for low power real time systems

Abstract

The work presented in this paper focuses on behavioral level power optimization. Specifically, we address the problem of scheduling a data-flow graph (DFG) under latency constraints. We have developed a revised integer linear program (ILP) model that minimizes both the peak power and the number of resources while satisfying timing constraints. Our modified integer linear programming (MILP) algorithm extends the traditional ILP approach, that minimizes, resources to include peak power considerations while adding extensions for multi-cycle and pipelined arithmetic components. To demonstrate the MILP algorithm's efficacy, two DFGs were examined: a second order differential equation solver (DiffEq) and a finite length impulse response filter (FIR). In our benchmark results, the peak power in DiffEq was reduced 25% after scheduling alone and reduced 50% after scheduling and pipelining were both applied. The FIR filter was reduced 63% after scheduling and reduced 75% after scheduling and pipelining.