A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test

Abstract

The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time. Since enabling only a subset of scan flip-flops to capture test responses in one cycle compromises the fault coverage, we propose a new method to reduce the fault coverage loss. First, we use a more accurate notion, spoiled nodes, instead of violation edges used in previous works to analyse the ependency of flip-flops, then we use simulated annealing(SA) mechanism to find the best combination of these flip-flops while considering the clock trees' impact. To the best of our knowledge, this is the first work to make shift and capture power in a controllable way with minimum fault coverage loss, small test-data volume and no extra hardware overhead for at-speed transition fault test. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed method.