A Novel Sample-and-Hold-Based Time-to-Digital Converter Architecture

Abstract

In this paper, the design of a time-to-digital converter (TDC) for measuring the time of flight (ToF) of a radio pulse is described. The novel idea is based on the adoption of a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">charge-pump</i> time-to-voltage transducer followed by a sample-and-hold amplifier (SHA) and by a second-order discrete-time incremental Delta-Sigma (¿¿) converter to perform a single-shot conversion. The TDC architecture is capable of achieving a range of 220 ns, a time resolution of about 200 ps (a 10-bit incremental ¿¿ converter), and robustness with respect to temperature variations. The design has been successfully verified through simulations both at system and transistor levels using a 0.25-¿m complimentary metal-oxide-semiconductor (CMOS) technology with a -2.5- to + 4-V power supply.