A Novel Recursive Filter Realization of Discrete Time Filters

Abstract

This paper presents a new Recursive Digital Filter (RDF) architecture for discrete time filters. This novel architecture allows decomposition of any discrete time filter into recursive filter of multiple order systematically. This decomposition results in reduction of the hardware when compared to conventional implementation. This hardware complexity reduction is feasible for both fixed and programmable filter coefficients. As an illustrative example, the hardware reduction is demonstrated for a programmable 100 tap symmetric FIR filter. Here, the complexity is quantified in terms of number of multipliers and adders with specific bit widths needed. Matlab numerical results are provided to compare the performance between the conventional and RDF implementation. The resources utilized in both architectures (conventional as well as RDF) are compared for Xilinx Kintex-7 FPGA device.