Abstract
In this paper, we adopt the Signed Digit (SD) number system and the Distributed Arithmetic (DA) computing scheme to achieve a novel design of high throughput recursive digital filters. The SD system enables a carry-propagation free addition as well as the most-significance-digit (MSD) first computation. Based on these properties, we devise a recursive computing scheme which successfully reduces the initiation interval to the delay of computing one digit instead of the entire word. Combined with the DA scheme, we can further exploit the bit-level parallelism while maintain a low circuit complexity. We design a Signed Digit Multi-Operand Adders (SDMA) array as the building block to implement the SD-DA algorithm. It can compute an inner product operation efficiently and suited well to VLSI implementation.
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