A Novel Reconfigurable Execution Core for Merged DSP Microcontroller

P.K Meher,A K Rath

doi:10.3844/jcssp.2007.803.809

Abstract

The study presents an execution core which can be reconfigured either for calculation of digital convolution or for computation of discrete orthogonal transform by appropriate local buffer initialization of processing cells. It is shown that the data flow pattern can be changed by a single bit control signal. The proposed core can be connected to port 1 of Intel 8051 to derive the necessary control signals for reconfiguration. The core can be used as a pluggable module with existing microcontroller when DSP algorithms are required to be implemented. Using such execution core the computational load of the processor can be significantly reduced as the math-intensive components of the DSP algorithm is relegated to the execution core. The use of such pipelined core will not only caters to the need of real-time performance, but also it will facilitate scalability, reusability and flexibility for wide varieties of DSP functionalities.

Highlights

Cellular phone, which must implement both supervisory tasks and voice-processing tasks
We have shown here that the run-time execution core presented in previous section for calculation of DOT and convolution can be used to realize a merged Digital signal processors (DSPs)-microcontroller architecture
In this paper we have presented a merged DSP microcontroller architecture, where math-intensive functions of algorithms are relegated to a DSP component comprised of a transform modules, a multiplier array storage modules and a data interface unit

Summary

Introduction

Cellular phone, which must implement both supervisory tasks and voice-processing tasks. Using a DSP for computation intensive digital signal processing simple microcontroller application is not a costalgorithms[1,2].

Results

Conclusion