A novel performance driven power gating based on distributed sleep transistor network

Abstract

Power Gating is an effective method to reduce leakage power. One of the most important issues in power gating design is the decision on the size of sleep transistor, which is mostly determined by the maximum instantaneous current (MIC) and the maximum tolerable voltage drop. In order to reduce the sleep transistor area, the distributed sleep transistor network (DSTN) was proposed to reduce MIC by connecting all the virtual ground nets together. Most of the following works focused on estimating the MICs through sleep transistors accurately. But the previous works use a pre-defined global voltage drop constraint on circuit, which leads to a uniform gate slowdown. In this paper, we propose a performance driven methodology for DSTN design, which exploits the maximum tolerable voltage drops of gates, particularly the non-critical ones, to reduce the total sleep transistor area without additional performance loss. Moreover, a clustering strategy in placement is proposed to help further reduce the total sleep transistor area. Experimental results show that the proposed approach can reduce the total sleep transistor area by about 36% on average.