Abstract
In this paper, we propose a new parallel segmentation scheme for the digital/time converter (DTC) which is employed in fractional-N digital phase-locked loops (PLLs) to cancel out the quantization error induced by the digital DS modulator. The proposed parallel scheme removes one redundant least-mean square (LMS) gain in compared with the conventional parallel one. Therefore, the design of the system becomes less complicated while guaranteeing a fast convergence speed of the LMS gains and a short DTC time range. The effectiveness of the proposed segmentation scheme is demonstrated via simulations of a digital PLL built at behavioral level and compared to the conventional segmentation schemes.
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