Abstract
Packet contention is a key issue in optical packet switch (OPS) networks and finds a viable solution by including optical buffering techniques incorporating fiber delay lines (FDLs) in the switch architecture. The present paper proposes a novel switch architecture for packet contention resolution in synchronous OPS network employing the packet circulation in FDLs in a synchronized manner. A mathematical model for the proposed switch architecture is developed employing packet queuing control to estimate the blocking probability for the incoming traffic. The switch performance is analyzed with a suitable contention resolution algorithm through the computer simulation. The simulation results substantiate the proposed model for the switch architecture.
Highlights
The growth of optical transmission technology in recent years is significant by achieving a Tbps class of transmission speed
Packet contention is a key issue in optical packet switch (OPS) networks and finds a viable solution by including optical buffering techniques incorporating fiber delay lines (FDLs) in the switch architecture
The present paper proposes a novel switch architecture for packet contention resolution in synchronous OPS network employing the packet circulation in FDLs in a synchronized manner
Summary
The growth of optical transmission technology in recent years is significant by achieving a Tbps class of transmission speed. The deflection routing exploits the space dimension to resolve contention It introduces delays in the data path and requires packet re-sequencing as packets may arrive out of order. Switch architecture designed in [13] uses a single level of FDLs i.e. all buffers are in shared mode This model performance degrades with the rise in arriving packet rate or requires more delay lines to reduce blocking probability. The switch hardware cost can be better managed with a proper node architecture design with a better contention resolution scheme involving flexible delay lines This design can be further modified to allow packet circulation in buffers or FDLs. This paper proposed a switch architecture that utilizes the delay lines in efficient way involving packet circulation to resolve the contention.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Communications, Network and System Sciences
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
