Abstract
A transistor with an orthogonal gate (OG) electrode is proposed to improve <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> capability, reduce the gate-to-drain overlap capacitance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ), and improve figure of merit (FOM). The OG has both a horizontal section and a vertical section for MOS gate control. This 30-V device is implemented in a 0.18-mum CMOS-compatible process. Comparing to a conventional extended drain MOSFET transistor with the same voltage rating and device size, four times higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> capability and 53% improvement in FOM are observed.
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