A novel optimization algorithm for Chien search of BCH Codes in NAND flash memory devices

Abstract

As NAND flash memory chips become denser, they are more vulnerable to random errors caused by ageing, read or write interference, and erase operations. These errors compromise both the data integrity and lifetime of flash memory so that error correction codes (ECC) are employed by the flash controller to strengthen the fault tolerance. The BCH (Bose Chaudhuri Hochquenghem) code is a widely used ECC technique in flash-based storage devices due to its strong error correction capability and high performance. The third step of decoding a BCH code is the Chien search process, which locates the errors in the received codeword. To increase the decoding throughput, parallel Chien search algorithms are used, but existing algorithms occupy more than 60% area of the total decoding logic, increasing the hardware complexity and energy consumption. To reduce the hardware complexity and overhead, in this paper, we propose a plane optimization algorithm to reduce the redundant XOR gates used in the Chien search process. Our study based on intensive experiments shows that for a (2047,1926, 11) BCH code with the parallel factor of 32, the proposed optimization algorithm reduces the number of XOR gates used in the Chien search process by 79%, 46% and 13%, respectively, compared to the straightforward implementation, the GMA approach and the strength-reduced architecture.