Abstract
With technology scaling, various degrading factors come up in the design, like short channel effects, noise, distortions etc. Improving noise performance is challenging at a lower technology node. This paper presents a design of two-stage CMOS operational amplifier at 32 nm technology node and two existing noise reduction techniques which are previously used at a higher technology node are implemented on this circuit to analyze the impact of noise at a lower technology node. Performance of three of the circuits is compared in terms of parameters like input and output noise voltage, gain, bandwidth etc.
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